1. Field of Invention
This invention relates generally to semiconductor memories and specifically to a PMOS based non-volatile memory latch.
2. Description of Related Art
Non-volatile latches are well known in the art and are used, for instance, to store addresses identifying defective memory locations, i.e., redundancy addresses. For example, a non-volatile latch for storing redundancy addresses is disclosed in U.S. Pat. No. 4,858,185, incorporated herein by reference. The latches described in that patent include NMOS floating gate memory cells. However, since NMOS memory cells require high programming and erasing voltages, the size to which these cells, and thus their associated latches, can be minimized is limited. Seeking to overcome this scaling limitation, some have proposed to employ PMOS memory cells in non-volatile latches, such as that disclosed in the commonly owned and co-pending U.S. patent application Ser. No. 08/778,802 entitled "A PMOS Non-volatile Latch for Storage of Redundancy Addresses" and filed on Jan. 3, 1997.
The above-referenced U.S. Patent Application teaches a PMOS non-volatile latch having two PMOS memory cells and a cross-coupled latch. The cross-coupled latch is formed by two PMOS memory cells PC3 and PC4 and two NMOS transistors MN1 and MN2, as shown in FIG. 1. The latch 10 is programmed to one of two binary states by forcing one of the two nodes D1 and D2 to a negative potential while holding the control gates of cells PC1 and PC2 at a constant positive potential. Forcing node D1 to the negative potential results in cell PC1 being programmed, wherein the latch 10 represents the first binary state, e.g., "1". Conversely, forcing node D2 to the negative potential results in cell PC2 being programmed, wherein the latch 10 represents the second binary state, e.g., "0".
Although requiring lower program voltages than earlier latches which employ NMOS cells, the latch 10 nevertheless requires the application of program and erase voltages in every storage operation, irrespective of the data's binary value. That is, to write a "1", cell PC1 is programmed, and to write a "0", cell PC2 is programmed. Accordingly, every storage operation requires the application of programming voltages and, in addition, is therefore limited by floating gate charge times. Further, cross-coupled latches, such as that employed in the prior art latch 10, is susceptible to fluctuations in the supply voltage which, in turn, may result in the latching of erroneous data.